1. Field of the Invention
The present invention relates to a display panel driving device that drives a display panel.
2. Description of Related Art
A liquid crystal display device includes a liquid crystal display panel. The liquid crystal display panel has a plurality of scan lines and a plurality of signal lines. The signal lines cross each of the scan lines. The liquid crystal display panel also has pixel units, which are formed at portions where the scan lines and signal lines cross each other. The liquid crystal display device also includes a display panel driving device. The driving device has a scan line driver, which supplies a selection signal to each of the scan lines, and a signal line driver, which supplies a pixel data signal to each of the signal lines.
The signal line driver is divided into a plurality of driver ICs (Integrated Circuits) (see FIG. 2 of Japanese Patent Application (Kokai) Publication No. 10-153760, for example). Each driver IC includes a semiconductor IC. The driver ICs are connected in cascade by a power line and a passage line (10). The power line extends along the driver ICs, and is connected to the passage line (10). The passage line (10) connects each two adjacent driver ICs. A clock line (CLK) is included in the passage line (10). The passage line (10) passes through the drivers IC, and is used to transmit a pixel data signal, a clock signal, and various control signals. Each driver IC (see FIG. 3 of Japanese Patent Application (Kokai) Publication No. 10-153760, for example) accepts a pixel data signal in synchronization with a clock signal supplied via the clock line (CLK) and a buffer (4). The driver IC then supplies the pixel data signal to a control logic CT. The control logic CT supplies to the signal lines of the liquid crystal panel a driving voltage corresponding to the pixel data signal.
Each driver IC receives the clock signal via the buffer (4) and sends the clock signal to a subsequent driver IC through another buffer (8) and the clock line (CLK). In this “subsequent driver IC,” the clock signal is supplied from the preceding driver IC via the clock line (CLK) and the buffer (4). This clock signal is then supplied to a next driver IC via the buffer (8) and the clock line (CLK).
As described above, a plurality of driver ICs are connected in cascade, and a clock signal is therefore transmitted through each driver IC. As a result, the duty ratio of the clock signal gradually changes. Therefore, the duty ratio of the clock signal in one driver IC could be different from the duty ratio of the clock signal in another downstream driver IC.
In order for the clock signal to be transmitted to the subsequent driver IC with the clock signal duty ratio kept at a constant level, a duty cycle regulator is provided in each driver IC (see FIG. 3 of Japanese Patent Application Publication No. 10-153760). The following duty cycle regulators have been proposed: a duty cycle regulator that uses a PLL (Phase-Locked Loop) circuit (see FIG. 4 of Japanese Patent Application Publication No. 10-153760); and a duty cycle regulator that uses a DLL (Delay Locked Loop) circuit (see FIG. 7 of Japanese Patent Application Publication No. 10-153760). If a duty cycle regulator is equipped with the PLL or DLL circuit in each driver IC, a clock signal supplied from a preceding driver IC undergoes a waveform shaping process in that driver IC and then transmitted to a next driver IC. Therefore, in all the driver ICs, the duty ratio of the clock signal remains unchanged at a constant level.
However, the PLL and DLL circuits are large in size, resulting in an increase in power consumption as well as in manufacturing costs.